Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to such an extent that integrated circuits have become widely incorporated in modern consumer electronics products. Such consumer electronics products include, but are not limited to, mobile phones, MP3 music players, personal computers, data storage devices, and portable navigation systems. It is known that the utility of many such consumer electronic products is increased when the non-volatile data storage capacity of these products is increased.
One of the key enablers of such advanced consumer electronic products, has been the improvements and advancements in non-volatile memory storage devices. In particular, the data storage capacity, i.e., the amount of data that can be stored, of flash memory devices has increased dramatically with the continued reduction in the physical size of transistors and interconnects. Further significant advances in non-volatile memory storage capacity have been achieved by the introduction of the NAND flash architecture. Recently, even further advances in non-volatile memory storage capacity have been achieved through the use of multi-level flash memory cell technology. A multi-level flash memory cell is a single field effect transistor structure with a floating gate, and associated write and read circuitry operable, respectively, to program at least four states, rather than the two states of a conventional flash memory cell, so that at least two bits worth of data may be stored and retrieved from a single flash memory cell.
Unfortunately, because the operating voltage range of the multi-level cell flash memory devices remains the same as the operating voltage range of single-level cell flash memory devices, the floating gate charge separation, and corresponding threshold voltage separation, between adjacent states in a multi-level flash memory cell are decreased as compared to the separation between states in a single-level flash memory cell. Since the margin of state separation is decreased in multi-level flash memory cells, the susceptibility to various error mechanisms is correspondingly increased, and must be dealt with by additional circuitry.
What is needed are methods of, and apparatus for, operating at least portions of a flash memory device, such as a multi-level cell NAND flash memory device, so as to reduce susceptibility to data decay and read disturb errors.